This material is based upon work supported by the National Science Foundation under Grant No. 0087487.

Any opinions, findings and conclusions or recomendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation (NSF).

Proposal

• Summary
• Description
• References

Year1 report

Year2 report

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Selected publications:

• H. Wang, M. Veeraraghavan, R. Karri, L. Tao, "Design of a High-Performance RSVP-TE Signaling Hardware Accelerator," to appear in IEEE Journal on Selected Areas in Communications (JSAC), special issue on Optical Communications and Networking (OCN), August 2005.
• M. Veeraraghavan, X. Zheng, W. Feng H. Lee, E. K. P. Chong & H. Li, "Scheduling and transport for file transfers on high-speed optical circuits," Journal of Grid Computing, vol. 1, issue 4, 2003, pp. 395-405.

• M. Veeraraghavan, H. Wang, "A Comparison of In-Band and Out-of-Band Transport Options for Signaling," 5th International Workshop on Optical Networking Technologies, Globecom 2004, Dec. 3, 2004, Dallas, TX.
• H. Wang, R. Karri, M. Veeraraghavan, and T. Li, "Hardware-Accelerated Implementation of the RSVP-TE Signaling Protocol," in Proc. of IEEE ICC2004, June 20-24, 2004, Paris, France.

• M. Veeraraghavan, H. Lee, E. K. P. Chong and H. Li, "A Varying-Bandwidth List Scheduling Heuristic for File Transfers," in Proc. of IEEE ICC2004, June 20-24, 2004, Paris, France.
• H. Lee, M. Veeraraghavan, H. Li and E. K. P. Chong, "Lambda Scheduling Algorithm for File Ttransfers on High-Speed Optical Circuits," International Symposium on Cluster Computing and the Grid (CCGrid 2004), April 19 - 22, 2004, Chicago, Illinois, USA.
• H.Wang, M.Veeraraghavan and R. Karri, "A Dynamic Circuits Based Wide-Area SAN Solution," 1st International Workshop on Optical Networking Technologies for Global SAN solutions, Oct. 13, 2002, Dallas, TX.

• H.Wang, M.Veeraraghavan and R. Karri, "A Hardware Implementation of a Signaling Protocol," in Proc. of Opticomm 2002, July 29-Aug. 2, 2002, Boston, MA.

 

Talks:

• Hardware-Accelerated Implementation of the RSVP-TE Signaling Protocol, ICC2004, June 20-24, 2004, Paris, France.

• Hardware Accelerated Signaling and its Application in Fast Network Restoration, CATT annual review, Nov. 2002, Polytechnic University.
• A Hardware Implementation of a Signaling Protocol, Opticomm 2002, July 29-Aug. 2, 2002, Boston, MA.

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Technical documents:

• Specification of a subset of GMPLS RSVP-TE for a hardware-accelerated implementation
• Detailed description of GMPLS RSVP-TE signaling procedures for hardware implementation
• Specification of a subset of GMPLS CR-LDP for a hardware-accelerated implementation
• Schematic Design Request
• Clock Architecture (PCB board)

Hardware/Software design files:

• Board schematic for a 64 by 64 SONET switch with hardware-accelerated
  GMPLS signaling created using the Cadence Concept HDL tool (tar file)
• Hardware Signaling Accelerator FPGA VHDL Source Code (zip file)
• Pin Assignment of the Hardware Signaling Accelerator FPGA (Xilinx XC2V3000-6BF957)(MS Excel file)

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Team:

• PIs:

• Malathi Veeraraghavan (mailto:mv@poly.edu)
• Ramesh Karri (ramesh@india.poly.edu)

• Research Scientist:

• Dr.Haobo Wang (mailto:haobo_w@photon.poly.edu)
• Dr.Xuan Zheng (mailto:xz3y@virginia.edu)
• Dr.Liji Wu (mailto:wulj@poly.edu)

• Graduate Students:

• Sevron Ghee (mailto:sghee01@utopia.poly.edu)
• Nikhil Joshi (mailto:njoshi01@utopia.poly.edu)

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Internal documents (for the team):

• Signaling protocol original description
• Final signaling specification (OSCP)
• PCI Specification 2.1
• Xilinx VirtexII FPGA (Xilinx)
• IDT71V2556S (IDT)
• IDT72V36100 (IDT)
• IDT75P52100 (IDT)
• VSC9182 (Vitesse)